Coming to Grips with Chips By Norm Hebert published: Monday, October 18 2004
Hoping that VMware’s hardware virtualization strategy will be unveiled at VMworld 2004
Any Wintel virtualization engineer who has had a good peek at the Micro-Partitioning functionality of the newly released IBM POWER5 processor will quickly realize that the future of x86 based server virtualization is likely to be hardware based.
According to IBM marketing documentation, this “revolutionary” RISC processor, which currently runs the Linux, AIX and legacy AS400 OS's, contains in excess of 276,000,000 transistors, has a dual core and can execute either 32 or 64 bit code at full speed, with no penalty when running 32 bit applications.
In addition to its dual core of two complete CPUs in each chip, IBM has also baked in what it calls SMT (Simultaneous Multi-Threading) technology. This makes each of the physical processors appear to the OS as dual physical processors, much as Intel’s HT (Hyper Threading) technology does.
Both SMT and HT technologies are design techniques used to keep the processor as busy as possible by giving it more than one thread to churn on. Within these implementations, even if one thread is waiting on memory or some other system resource, other threads are ready to use these idle system resources.
However, IBM’s SMT is more sophisticated and more capable than Intel’s HT. With SMT threads can actually be bounced between the POWER5’s dual cores, whereas currently HT is only shipping on single core P4 and Xeon processors. IBM has expanded the POWER5’s die geography by over 24% to accommodate SMT-specific logic and resources. In contrast, Intel grew their die by only 5% when they implemented HT.
The most compelling feature of the POWER5 architecture from a virtualization standpoint is Micro-Partitioning, which can allow a single physical processor to be divided up into 10 virtual processors, each capable of running a different OS. Previous pSeries class machines based on the POWER4 and earlier chips were able to implement logical partitions (LPARs), but granularity was limited to the CPU level. So a dual processor machine could run AIX in one partition using processor one and LINUX in a second partition built around the second processor.
Now, conceivably, on a 4-CPU system with dual cores and SMT, an Administrator could create up to 160 logical partitions each capable of running a discreet OS. In addition, these partitions are dynamically scalable both up and down on the fly without the need for booting either the host or the guest. This flexibility is at the heart of IBM’s “Capacity on Demand” initiative.
For example, let’s say that we have a customer with a website hosted on Apache and running inside a Linux VM on one of these POWER5 based machines. And let us say that the website owner is the organization which hosts an unnamed major annual UK tennis tournament.
The customer has the need to make its website available all year long, so let’s say that they lease .2 processors to run their steady state operations. This customer is going to get 99.9+% of its yearly Web hits during a ten-day period in June when the tournament is in process, and then after is going to return to more-or-less steady state operations.
With dynamic LPAR-enabled Capacity on Demand, this web server VM can dynamically be assigned an additional 15.8 units of processor, together with additional memory and network resources as necessary, to handle the additional workload for those ten days. Then it will have the capability to seamlessly step back down to its steady state operations at .2 processors, with less memory and network resources, until the following June. That is the concept behind “Capacity on Demand,” purchasing only the capacity that you need and then only for when you need it.
Intel has recently announced its own dual-core server effort called Silverdale, which is said to implement many of these same types of hardware virtualization schemes. Intel has reported that Silverdale technology will be implemented on upcoming versions of its Xeon and Itanium processors starting in late 2005 or early 2006, roughly coincidental with Microsoft’s release of its Longhorn OS. OS tweaks will be required to exploit the virtualization capabilities of the new Silverdale chips.
Microsoft is currently sitting at the table and working hand-in-hand with Intel to develop the code necessary to optimize the virtualization of OS instances using this new Silverdale hardware. Microsoft’s Virtual Server should be ready to take advantage of this technology immediately upon the release of Longhorn. VMware, however, has been tight-lipped about its future hardware virtualization efforts, and many of us are hoping that this strategy will be unveiled at the VMware conference later this month.
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Norm Hebert is employed as the chief Windows Network Architect and Server/Storage Virtualization Specialist by Certified Network Consultants of Nashua NH and is currently on assignment with IBM Global Services. Mr. Hebert is an IBM certified TotalStorage™ Networking and Virtual Infrastructure Specialist, is fully both Microsoft and VMware certified, and can be reached at:
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